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TMC3211
Integer Divider
32-Bit, 20 MOPS Features
* 32-bit by 16-bit fixed-point integer division with 32-bit quotient * 20 MHz clock rate and pipelined throughput rate * Three-bus I/O architecture allows unrestricted throughput * Easy system interfacing * Status flags for divide-by-zero and inexact result * All inputs and outputs TTL compatible Data is input on separate busses, and quotients are available on a 32-bit output bus with synchronous three-state enable. All data inputs and outputs are registered and TTL compatible. All input and output signal timing is referenced to the rising edge of Clock. The TMC3211 has a single system clock and separate load enable controls for the dividend and divisor registers. This allows the device to be used in applications requiring division by a constant. Underflow automatically produces the expected zero quotient, and dividing by zero sets a divideby-zero output flag. The internal architecture of the TMC3211 allows all 32-bit two's complement integer dividends and nonzero 16-bit two's complement integer divisors, without prenormalization. The output quotient format is 32-bit integer. The TMC3211 makes a full-precision, full-speed divide function available to designers of workstations, image processors, and radar systems who need to perform perspective extractions, matrix operations, range scaling, and other complex functions.
Applications
* * * * * Graphics and image processors Matrix operations and geometric transforms Perspective extraction Radar signal processing Range scaling
Description
The TMC3211 is a fast monolithic two's complement integer divider which can divide a 32-bit dividend by a 16-bit divisor to produce a 32-bit quotient, with a maximum pipelined throughput of 20 MOPS (Million Operations Per Second).
Block Diagram
X15-0 16 ENX CLK 1 Divisor 16 X31-0 32 Dividend 32 ENY
2-18
16 - Stage Non-Restoring Divider 32 Flags
19
Quotients 32
20 OE 32 Q31-0 2 DZERO, INX
REV. 1.0.1 5/9/00
PRODUCT SPECIFICATION
TMC3211
Functional Description
General Information
The TMC3211 consists of input registers, a pipelined array divider, and output (quotient) registers. The 16-bit divisor and 32-bit dividend input registers can each be loaded independently using the two synchronous load enable controls. The divider is a 16-stage pipelined non-restoring array which produces a 32-bit quotient and condition flags which indicate an attempted division by zero, or operations which yield a non-zero remainder or inexact result.
The 32-bit parallel quotient output register includes three-state output drivers with synchronous enable control, which permits multiple TMC3211s to be operated in parallel or connected directly to a system bus. The TMC3211 requires a total of 19 clock cycles to generate a full 32-bit quotient result. Once the internal pipeline is full, a new quotient is available at the output every clock cycle.
Pin Assignments
NMLKJHGFEDCBA Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 TOP VIEW CAVITY UP A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 Name GND Y14 Y13 VDD Y9 Y6 Y5 Y2 REM Q0 Q3 Q6 VDD YEN Y15 VDD Y12 Y10 Y7 Y3 Y1 DZ Q2 Q4 Q7 Q8 Y16 VDD VDD GND Pin C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 Name Y11 Y8 Y4 Y0 Q1 Q5 GND GND Q9 Y18 Y17 GND VDD Q10 Q11 Y20 Y19 GND GND Q12 Q13 Y22 Y21 VDD VDD Q14 Q15 Y23 GND VDD Pin G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 H1 H2 H3 H11 H12 H13 L1 L2 L3 L4 L5 L6 L7 L8 L9 Name Q17 VDD Q16 Y24 Y25 GND GND Q19 Q18 Y26 Y27 VDD VDD Q21 Q20 Y24 Y25 GND GND Q19 Q18 Y30 VDD GND VDD GND X8 VDD X15 Q31 Pin L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 Name Q27 VDD GND Q24 Y31 X0 X2 X4 X6 X9 X11 X14 CLK Q30 GND GND Q25 GND X21 X3 X5 X7 X10 X12 X13 XEN OEQ Q29 Q28 Q26
2
REV. 1.0.1 5/9/00
TMC3211
PRODUCT SPECIFICATION
Pin Descriptions
Signal Type Power Signal Name VDD Pin Number B3, A4, A13, D11, F11, G12, J11, K11, L11, L7, L4, L2, J3, G3, F3, C2, C3 A1, C4, C11, C12, E11, H11, L12, M12, M11, L5, L3, N1, K3, H3, G2, E3, D3 M9 System Clock. The TMC3211 has a single Clock input. All input and output signal timing is referenced to the rising edge of Clock. Dividend Data. The 32-bit Dividend is presented through the registered Y input port. Y31 is the sign bit. The LSB is Y0. Divisor Data. The 16-bit Divisor is presented through the registered X input port. X15 is the sign bit. The LSB is X0. Quotient Data. The current Quotient is available on the registered Q output bus. Q31 is the sign bit. The LSB is Q0. Description Supply Voltage, Ground. The TMC3211 operates on a single +5V supply. All power and ground lines must be connected.
GND
Clock
CLK
Inputs
Y31-0
M1, L1, K2, K1, J2, J1, H2, H1, G1, F1, F2, E1, E2, D1, D2, C1, B2, A2, A3, B4, C5, B5, A5, C6, B6, A6, A7, C7, B7, A8, B8, C8 U8, M8, N8, N7, M7, N6, M6, L6, NS, MS, N4, M4, N3, M3, N2, M2 L9, M10, N11, N12, L10, N13, M13, L13, K12, K13, J12, J13, H12, H13, G11, G13, F13, F12, E13, E12, D13, D12, C13, B13, B12, A12, C10, B11, A11, B10, C9, A10 B1
X15-0
Outputs
Q31-0
Controls
YEN
Dividend Write Enable. Data present at the Dividend input Y31-0 is latched into the input registers on the rising edge of clock when the enable control YEN is LOW. Divisor Write Enable. Data present at the Divisor input X15-0 is latched into the input registers on the rising edge of clock when the enable control XEN is LOW. Quotient Output Enable. The quotient output bus Q31-0 and flags DZ and REM are in the high-impedance state when the registered Output Enable OEQ is HIGH. When OEQ is LOW, they are enabled on the next clock cycle. Divide-By Zero Flag. When a zero divisor is input, the resulting invalid output quotient will be accompanied by a registered Divide-By-Zero Flag HIGH. Inexact Remainder Flag. Whenever a division operation leaves a nonzero remainder, the resulting qotient is accompanied by a registered nonzero Remainder Flag HIGH. Index Pin (optional)
XEN
N9
OEQ
N10
Flags
DZ
B9
REM
A9
No Connect
D4
REV. 1.0.1 5/9/00
3
PRODUCT SPECIFICATION
TMC3211
Applications Discussion
Division Using A Constant
By utilizing the separate input data register load enable controls, the TMC3211 can perform division by a constant. The data currently held remain in the input registers until updated by the user.
Data Formats
The TMC3211 supports fixed-point two's complement data formats. By keeping track of the binary points of the input data, the user can then interpret the resulting quotient properly. Two possible binary weightings of the input and output bits are as follows:
Pin D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 Y X Q -231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 -231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 -215 215 214 214 214 213 213 213 212 212 212 211 211 211 210 210 210
D9 29 29 29
D8 28 28 28
D7 27 27 27
D6 26 26 26
D5 25 25 25
D4 24 24 24
D3 23 23 23
D2 22 22 22
D1 21 21 21
D0 20 20 20
Figure 1. Integer Data Format
Y X Q
-20
.2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 -20 .2-1 2
-2
2-2 2
-3
2-3 2
-4
2-4 2
-5
2-5 2
-6
2-6 2
-7
2-7 2
-8
2-8 2
-9
2-9 2
-10
2-10 2-11 2-12 2-13 2-14 2-15 2-11 2-12 2-13 2-14 2-15 2-16
-2
15
.2
14
2
13
2
12
2
11
2
10
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
Figure 2. Fractional Data Format
where a leading minus sign indicates a sign bit. Care must be taken when adopting fractional data formats. By observing the binary weighting applied to the input data in the dividend and divisor, the binary point of the quotient can then be correctly established. The difference lies only in constant scale factors, which must be considered in order to maintain a data format which is compatible with the bit weighting of the hardware system. The two most common choices are fractional and integer notation. If integer notation is used, the LSBs of the dividend, divisor, and quotient all have the same value. With fractional notation the MSBs are all of equal weight.
Inexact Results
The flag REM is provided to indicate that the current quotient left a nonzero remainder and was truncated toward zero.
Negative Full-Scale Overflow
Due to a finite data word width, a two's complement overflow error occurs under the following unique condition: Divisor Y=80000000H (- Full-Scale) Dividend X=FFFFH (-1) Result: Quotient Q=80000000H (- Full-Scale) As stated above, this is due to a limitation in the number of bits available to indicate a positive full-scale quotient, and data overflows into the MSB position to indicate an incorrect sign.
Divide by Zero
The flag DZ indicates that the divisor input for the current calculation was a zero, independent of the dividend. Dividing by zero is an undefined operation yielding a meaningless quotient. Thus, this flag must be monitored to guard against possible errors.
4
REV. 1.0.1 5/9/00
TMC3211
PRODUCT SPECIFICATION
1 CLK tS Y31-0 Y0 tH Y1
tPWH 2 tCY
tPWL 3 19 20 21
Y2 Note 1
X15-0
X0
X1
XEN
YEN tD Q31-0, DZ, REM2 Notes: 1. Demonstrates division by a constant, Q2 = Y2/X1. 2. Assumes OEQ = Low. Q0 tHO Q1 Q2
Figure 3. Timing Diagram
VDD
VDD
n Substrate D1 Control Input p+ 1k n+ n n p p
n Substrate
D1 p+ Output n+ D2 p Well
D2 p Well
GND
GND
Figure 4. Equivalent Input Circuit
Figure 5. Equivalent Output Circuit
REV. 1.0.1 5/9/00
5
PRODUCT SPECIFICATION
TMC3211
Absolute Maximum Ratings (beyond which the device may be damaged)1
Parameter Supply Voltage Input Voltage Output Applied Voltage2 Forced Current Temperature
3,4
Min -0.5 -0.5 -0.5 -3.0 -60
Max +7.0 VDD + 0.5 VDD + 0.5 6.0 1 +130 175 300
Units V V V mA sec C C C C
Short-circuit duration (single output in HIGH state to ground) Operating, case Junction Lead, soldering (10 seconds) Storage -65
+150
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range, and measured with respect to GND. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
Operating Conditions
Temperature Range Parameter VDD VIL VIH IOL IOH tCY tPWL tPWH tS tH TA Supply Voltage Input Voltage, Logic LOW Input Voltage, Logic HIGH Output Current, Logic LOW Output Current, Logic HIGH Cycle Time Clock Pulse Width, LOW Clock Pulse Width, HIGH Input Setup Time Input Hold Time Ambient Temperature, Still Air VDD = Min VDD = Min VDD = Min 15 15 12 6 0 70 2.0 4.0 -2.0 50 Test Conditions Min. 4.75 Standard Nom. 5.0 Max. 5.25 0.8 V V V mA mA ns ns ns ns ns C Units
6
REV. 1.0.1 5/9/00
TMC3211
PRODUCT SPECIFICATION
DC Characteristics within Specified Operating Conditions1
Temperature Range Parameter IDDQ IDDU IIL IIH VOL VOH IOZL IOZH IOS Cl CO Supply Current, Quiescent Supply Current, Unloaded Input Current, Logic LOW Input Current, Logic HIGH Output Voltage, Logic LOW Output Voltage, Logic HIGH Hi-Z Output Leakage Current, Output LOW Hi-Z Output Leakage Current, Output HIGH Short-Circuit Output Current Input Capacitance Output Capacitance Test Conditions VDD = Max, VIN = 0V VDD = Max, OEQ = 5V, f = 20MHz VDD = Max, VIN = 0V VDD = Max, VIN = VDD VDD = Min, lOL = Max VDD = Min, lOH = Max VDD = Max, VIN = 0V VDD = Max, VIN = VDD VDD = Max, Output HIGH, one pin to ground, one second duration max. TA = 25C, f = 1MHz TA = 25C, f = 1MHz 2.4 -40 40 -150 10 10 Standard Min. Max. 5 150 -10 10 0.4 mA mA A A V V A A mA pF pF Units
Note: 1. Actual test conditions may vary from those shown, but guarantee operation as specified
AC Characteristics within Specified Operating Conditions
Temperature Parameter tD tHO Output Delay1 Test Conditions VDD = Min, CLOAD = 25pF VDD = Max, CLOAD = 25pF 5 Standard Min Output Hold Time Max 35 ns ns Units
Note: 1. Equivalent to tDIS and tENA of the three-state outputs
REV. 1.0.1 5/9/00
7
PRODUCT SPECIFICATION
TMC3211
Mechanical Dimensions
120-Pin Ceramic Pin Grid Array--G1 Package
Symbol A A1 A2 oB oB2 D D1 e L L1 M N P Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Pin diameter excludes solder dip finish. 3. Dimension "M" defines matrix size. 4. Dimension "N" defines the maximum possible number of pins. 2 2 SQ 5. Orientation pin is at supplier's option. 6. Controlling dimension: inch.
.080 .160 .040 .060 .125 .215 .016 .020 .050 NOM. 1.340 1.380 1.200 BSC .100 BSC .110 .145 .170 .190 13 120 .003 --
2.03 4.06 1.01 1.53 3.17 5.46 0.40 0.51 1.27 NOM. 33.27 35.05 30.48 BSC 2.54 BSC 2.79 3.68 4.31 4.83 13 120 .076 --
3 4
A2 A1 L D e oB oB2 P
A
Top View Cavity Up
D1
Pin 1 Identifier
8
REV. 1.0.1 5/9/00
TMC3211
PRODUCT SPECIFICATION
Mechanical Dimensions
120-Pin Plastic Pin Grid Array--H5 Package
Inches Min. A A1 A2 oB oB2 D D1 e L M N P Max. Millimeters Min. Max. Notes: Notes 1. Pin #1 identifier shall be within shaded area shown. 2. Dimension "M" defines matrix size. 3. Dimension "N" defines the maximum possible number of pins. 4. Controlling dimension: inch.
Symbol
.080 .125 .040 .060 .105 .180 .017 .020 .050 NOM. 1.340 1.350 1.200 BSC .100 BSC .120 .140 13 121 .003 --
2.03 3.18 1.02 1.52 2.67 4.57 0.43 0.51 1.27 NOM. 34.04 35.05 30.48 BSC 2.54 BSC 3.05 3.56 13 121 .076 -- 2 3
A2 L oB e A1 oB2 D P
A
D1
Bottom View
Top View
Pin 1 Identifier Beveled Corner Vendor Option
REV. 1.0.1 5/9/00
9
PRODUCT SPECIFICATION
TMC3211
Ordering Information
Product Number TMC3211H5C TMC3211G1C Temperature Range 0 to 70C 0 to 70C Screening Commercial Commercial Package 120 Pin Plastic Pin Grid Array 120 Pin Ceramic Pin Grid Array Package Marking 3211H5C 3211G1C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/9/00 0.0m 002 Stock#DS30003211 2000 Fairchild Semiconductor Corporation

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